1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a circuit for setting, to a test mode, a semiconductor circuit device capable of a test mode operation. More specifically, the present invention is related to a test mode setting circuit of such a semiconductor memory device.
2. Description of the Background Art
In a semiconductor integrated circuit device such as a dynamic random access memory (DRAM), in general, in the manufacturing process, tests are performed for checking whether normal operation can be implemented or not. Such tests include a screening test (burn-in test) for revealing a latent defect, a margin test for detecting margin defect of voltage or signal timing, and others. In such tests, a special chip operation (operation of a semiconductor integrated circuit device) that is not used in an actual use is performed, such that the semiconductor integrated circuit device is operated under a condition of high temperature and high voltage, or at a timing different from a normal operating timing. Such special chip operation is enabled by setting a test mode.
FIG. 8 is a schematic representation of an overall arrangement of a DRAM as an example of a conventional semiconductor integrated circuit device. In FIG. 8, a DRAM 100 includes a memory cell array 101 having memory cells MC arranged in a matrix of rows and columns, a word line WL provided corresponding to a row of memory cells, and a bit line BL disposed corresponding to a column of memory cells MC; a row decoder 102 for driving, to a selected state, a word line corresponding to an addressed row in memory cell array 101 according to an applied X signal; a sense amplifier 103 for sensing, amplifying and latching data of memory cells connected to a selected row; a column decoder 104 for selecting an addressed column of memory cell array 101 according to an applied Y signal.
DRAM 100 further includes a /RAS buffer 105 for taking in an externally applied row address strobe signal /RAS in synchronization with an internal clock signal CLK to generate internal signals ZRASE and int.RAS; a /CAS buffer 106 for taking in a column address strobe signal /CAS applied from an outside in synchronization with internal clock signal CLK to generate an internal column address strobe signal int.CAS; a /WE buffer 107 for taking in a write enable signal /WE applied from an outside in synchronization with internal clock signal CLK to generate an internal write enable signal int.WE; a row address buffer 108 for taking in an externally applied address in synchronization with an internal clock signal; a column address buffer 109 for taking in an externally applied address in synchronization with the internal clock signal; a row-related control circuit 110 for generating an X address according to an address signal from row address buffer 108 in response to activation of a row-related activation signal ZRASE from /RAS buffer 105; a column-related control circuit 111 for generating a Y address according to an address signal from column address buffer 109 upon activation of a column select activation signal (only the path is shown) from /CAS buffer 106; a write control circuit 112 for generating a write/read control signal according to a write/read instruction signal (only the path is shown) from /WE buffer 107; and an input/output circuit 113 for inputting and outputting data between an internal data line I/O and the outside according to the write/read control signal from write control circuit 112.
The column select activation signal is generated according to internal column address signal int.CAS, while the write/read control signal is generated according to internal write enable signal /WE.
A column select circuit that connects, to an internal data line I/O, a bit line corresponding to a selected column of memory cell array 101 according to a column select signal from column decoder 104 is arranged adjacent to sense amplifier 103. The column select circuit, however, is not shown in the drawing for simplicity purpose.
Input/output circuit 113 includes a preamplifier 113a for amplifying data on internal data line I/O when activated, an output buffer 113b for buffering internal data amplified by preamplifier 113a to generate external read data DQ in a data read mode, an input buffer 113d for buffering write data DQ received from an outside in data write operation, and a write driver 113c activated according to the write/read control signal from write control circuit 112 for driving an internal data line I/O according to write data from input buffer 113d. 
DRAM 100 further includes an internal voltage generating circuit 114 for generating internal voltages Vdd, Vbb, and Vcp according to an externally applied external power-supply voltage or an internally generated internal power-supply voltage, a clock buffer 115 for buffering a clock signal ext.CLK applied from an outside to generate an internal clock signal CLK, and a mode setting circuit 120 for generating a mode setting signal TM for designating a specific operation mode according to internal control signals int.RAS, int.CAS, and int.WE from buffers 105 to 107 and an external address signal bit.
Voltage Vdd is an internal power-supply voltage generated by down-converting an external power-supply voltage in internal voltage generating circuit 114. Voltage Vbb is a negative voltage generated through a charge pump operation in internal voltage generating circuit 114, and is applied to a substrate region of memory cell array 101 and other. Voltage Vcp is a voltage applied to a cell plate of a capacitor included in a memory cell MC. Internal voltage generating circuit 114 further generates a bit line equalizing voltage Vb1 for precharging a bit line BL in a standby cycle, a high voltage Vpp transmitted on a selected word line WL, and such.
Mode setting circuit 120 determines that a special mode is designated when internal control signals int.RAS, int.CAS, and int.WE and a specific external address signal bit satisfy a prescribed condition, and generates a mode setting signal TM for performing a designated mode. Mode setting circuit 120 contains a mode register for setting an operation condition (burst length, CAS latency, and the like) of DRAM 100.
In DRAM 100 as shown in FIG. 8, with mode setting circuit 120, a burn-in test mode is set up when a burn-in test which is one of the screening tests is to be performed. In the burn-in test mode, the voltage levels of internal power-supply voltage Vdd, a cell plate voltage Vcp, a high voltage Vpp (not shown), a bit line precharge voltage Vb1 and other from internal voltage generating circuit 114 are set higher than the respective voltage levels under normal operation conditions, in order to accelerate voltage stress. Moreover, in such burn-in test, more word lines than those selected in a normal operation mode are selected simultaneously in memory cell array 101.
Setting of these voltage conditions and setting of selecting conditions of word lines are performed individually using a specific set of externally applied address bits (address key).
FIG. 9 is a schematic representation of an arrangement of mode setting circuit 120 shown in FIG. 8. In FIG. 9, mode setting circuit 120 includes a level detection circuit 121 for detecting whether a signal BA0 of a specific node is set to a prescribed voltage condition; an MRS detection circuit 122 for detecting whether internal control signals int.RAS, int.CAS, int.WE satisfy a predetermined condition such as a WCBR (WE, CAS before RAS) condition; an address key detection circuit 123 for detecting whether a prescribed set of externally applied address signal bits A0 to An satisfy a prescribed state; and a mode detection circuit 124 for activating a test mode instruction signal TEM when an output signal BA0S from level detection circuit 121, an output signal MRS from MRS detection circuit 122, an address key detection signal ADK from address key detection circuit 123, and a specific bit signal bit A7 are all activated.
Level detection circuit 121 drives its output signal BA0S to the active state when a super VIH condition (SVIH condition) is satisfied in which, for example, a bank address signal bit BA0 is set at a higher voltage level than a normal logic high or H level (external power-supply voltage level) supplied during normal operation. Here, in FIG. 8, memory cell array 101 is divided into a plurality of banks that can be activated/inactivated for a row select operation independently from each other, and bank address signal bit BA0 is applied externally to specify one of these banks.
MRS detection circuit 122 determines that the WCBR condition is satisfied, or determines that a mode register set command is applied, when internal control signals int.RAS, int.CAS, and int.WE are all in the active state of the H level at the rising edge (or falling edge) of internal clock signal CLK, and drives a mode register set command detection signal MRS to the active state.
Address key detection circuit 123 receives predetermined address signal bits of the address bits A0 to An, and activates, when the received address signal bits are set to prescribed logic states, address key detection signal ADK to the active state. Mode detection circuit 124 is formed by an AND circuit, for example, and activates test mode instruction signal TEM when these signals BA0S, MRS, ADK, and A7 are all activated.
An address key is predetermined for each test operation mode. Thus, address keys differ for each of the test operation modes, such as a test operation mode in which internal power-supply voltage Vdd is boosted to a higher voltage level, a test operation mode in which a voltage level of high voltage Vpp transmitted on a word line is raised to a further higher level, a test operation mode in which a voltage level of cell plate voltage Vcp is raised to a level higher than the normal operation level, and a test operation mode in which the number of word lines selected simultaneously is increased and other test modes. Consequently, when a test mode is entered and a test is to be performed with a plurality of test conditions set concurrently, there is a need to set the address keys according to separate test operation modes to designate these test operation modes sequentially.
FIG. 10 is a diagram representing an example of a sequence of test operation mode entry in a conventional DRAM. Referring to FIG. 10, a test mode entry operation is first performed in order to set the DRAM into a test mode. Upon the test mode entry operation, as a command applied externally, mode register set command MRS is supplied together with a specific address signal bit A7, and a bank address signal bit BA0 is set to the super VIH (SVIH) condition, and an address key is set to a specific address key KY0. According to this test mode entry command, a test mode instruction signal TE is activated, and the DRAM is set to a state in which it can accept test mode instruction signals for designating separate test operation modes, to operate in various test operation modes for testing.
Thereafter, individual test operation mode for performing an actual test is designated. First, in order to set a test A, mode register set command MRS including address signal bit A7, and an address key KYA and bank address signal bit BA0 set to the super VIH (SVIH) condition are applied. As a result, output signals from the detection circuits 121 to 123 shown in FIG. 9 are all activated, and a test mode detection signal TEMA for enabling a test mode A from mode detection circuit 124 attains the active state. Test A is executed in this state.
Now, it is supposed that test A is a test operation mode in which an internal power-supply voltage is raised to a higher level than a normal voltage level in a normal operation. In this state, if a test B is to be set next, mode register set command MRS including address signal bit A7, bank address signal bit BA0 set to the super VIH (SVIH) condition, and an address key KYB are applied simultaneously. Consequently, a test mode designating signal TMB for enabling test B from mode detection circuit 124 provided corresponding to a test operation mode B attains the active state. As a result, in a test mode, both test A and test B can be executed concurrently.
Therefore, when the DRAM is to be operated under a plurality of test conditions, the test mode entry operation is performed, and thereafter, test A, test B, and other(s) are sequentially and serially designated.
Such test mode is an operation mode that a manufacturer performs in order to guarantee reliability of the products, and that a user never uses the test mode. In addition, in a test operation mode, a special operation is executed that is not used during a normal operation mode. Thus, for setting of a test mode, a manufacturer requires conditions other than normal operation conditions, such as a mode register set command including a specific address signal bit, an address key, a super VIH (SVIH), and others as described above so as to prevent the DRAM from erroneously entering a test mode while the DRAM is used by a user.
As described above, in a test mode, application of a high voltage referred to as a super VIH (SVIH) becomes necessary for entry into each test operation mode. Level detection circuit 121 in FIG. 9 discriminates the super VIH (SVIH) condition using the internal voltage as a reference. For example, bank address signal bit BA0 applied externally is down-converted using a diode element, for example, and the voltage level is determined as being at the H level, or at a logic low or L level. Thus, as shown in FIG. 10, when test A is entered and the internal voltage is set to a high voltage, and then test B is to be entered, there is a need to make the voltage level of a specific signal (bank address signal bit) BA0 sufficiently higher than the internal voltage in order to satisfy the super VIH condition. For example, in FIG. 11, a case is assumed in which the voltage level of internal power-supply voltage Vdd is set, for example, to 5.0 V when test A is entered, with the condition that the super VIH condition is a high voltage Va higher than a power-supply voltage Vdd of 3.3 V, for example, during a normal operation. If an inverter circuit is utilized for detection of the super VIH condition, an input logical threshold voltage of the inverter circuit also rises in proportion to internal power-supply voltage Vdd. In this case, the following relation need be satisfied:
SVIHxe2x88x92Vdrop greater than Vdd/2=input logical threshold voltage of the inverter. 
Here, Vdrop indicates a voltage drop of a specific signal (bank address signal bit) BA0 applied externally in the level detection circuit, and SVIH indicates a voltage of super VIH condition. For an accurate detection of the SVIH condition, the following relation is required:
SVIH greater than Vdrop+Vdd. 
Thus, if SVIH is at 6.3 V when power-supply voltage Vdd is at 3.3 V, voltage SVIH need be set to 8 V when power-supply voltage Vdd rises to 5 V.
Thus, when the voltage level of internal power-supply voltage Vdd is made higher, the voltage level of voltage SVIH satisfying the super VIH condition also becomes higher accordingly. In addition, in a case where the super VIH condition is set to twice the internal power-supply voltage Vdd using a voltage dividing circuit and the like, the voltage Va in FIG. 11 becomes 2xc2x7Vdd. If the voltage level of this internal power-supply voltage Vdd is set in a test operation mode to 1.5 times the voltage level of the normal operation, for example, a voltage of 2xc2x7Vdd=3xc2x7Vdd (Va) need be applied as the voltage Vb in order to implement the voltage SVIH that satisfy the super VIH condition at this time. In other words, there arises a need to apply voltage Vb of the voltage level that is three times the voltage Va that satisfies the super VIH condition in a normal operation mode.
The specific signal (bank address signal) is also applied to other buffer circuits (row address buffer 108 and column address buffer 109) as shown in FIG. 8, and therefore, the reliability of these buffer circuits would be lost when a voltage of such a high level is applied. Thus, in order to avoid such a risk, such special entry operations are conventionally performed as entering into a test mode without an application of a voltage satisfying the super VIH condition (without requiring the super VIH condition), and entering into the test operation mode with an internal voltage temporarily lowered, and then the internal voltage is raised again after the entry into the test operation mode.
When the super VIH condition is not required, however, there is a greater possibility of the DRAM erroneously entering into a test mode during the practical, actual use by a user. Moreover, in a case where a test mode is entered into by lowering an internal voltage temporarily to satisfy the super VIH condition, it takes a long time for the internal voltage to rise to the original level again after it has been lowered, so that the test time becomes longer, resulting in a degraded test efficiency.
An object of the present invention is to provide a semiconductor device that is capable of performing a test efficiently while suppressing the possibility of an erroneous entry into a test mode on a user side.
Another object of the present invention is to provide a semiconductor device capable of entering into a desired test operation mode with accuracy without degrading test efficiency, while suppressing the possibility of an erroneous entry into a test mode on the user side.
In brief, according to the present invention, a prescribed voltage condition required for an entry into a test operation mode is set selectively to a valid or invalid state.
By forcibly satisfying the state in which a prescribed voltage condition such as a super VIH, the need of setting a specific voltage condition such as super VIH under a special voltage condition such as under a high voltage condition and the need of changing an internal voltage and others can be eliminated, so that a prescribed operation such as a test can be performed by efficiently entering into a specific designated operation mode such as a test mode. In a non-forced state, the specific voltage condition becomes necessary, so that a specific voltage condition for entering into a specific operation mode such as a test mode would be required, which prevents an erroneous entry into an erroneous specific operation mode by a user.
In addition, when the test mode entry is performed in a serial access sequence, by making a specific voltage condition programmable for each test mode, a test mode entry can be effected without setting a specific voltage condition such as a super VIH in a test mode so that a successful entry into a test mode can be ensured to perform a test efficiently, while an erroneous entry into a test mode on the user side can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.